1. Field of the Invention
The present invention relates to a skew logic circuit device for use in a semiconductor memory device. More particularly, it relates to a skew logic circuit device which prevents the disable path of an output signal caused by buffering an input signal, from responding slowly.
2. Discussion of Related Art
As shown in FIG. 1, a conventional circuit of an input buffer which funtions a skew logic operation, comprises first to fifth inverters (IV1 to IV5), which are, in series, connected with one another, between an input terminal (IN) and an output terminal (OUT).
Generally, the inverters are composed of two CMOS-type transistors, and operate as a buffer for buffering an input signal from the outside. Suppose that an NMOS-type transistor of the first, third, and fifth inverters (IV1, IV3, and IV5) is larger in size than PMOS-type transistor, and a PMOS-type transistor of the second and fourth inverters (IV2 and IV4) is larger in size than a NMOS-type transistor.
The operation of the inverters constructed as indicated above will be described, referring to FIG. 2 showing operation timing. If (a) pulse signal is inputted to the input terminal (IN), a (b) pulse signal inverted through the first inverter (IV1) is transmitted to a first node (N1). The (b) pulse signal is quickly transmitted at the enable path, but slowly transmitted at the disable path. (c) to (f) pulse signals of FIG. 2 are the pulse signals at the respective nodes, which are outputted through the second to fifth inverters (IV2 to IV5). When we compare the (f) pulse signal which is outputted to the output terminal (OUT) with the (a) pulse signal which is inputted to the input terminal (IN), the pulse width of the (f) pulse signal which is an output signal, is much broader than that of the (a) pulse signal which is an input signal. This is because the pulse signal which is outputted through the respective inverters (IV1 to IV5), is transmitted quickly at the enable path, but slowly at the disable path, so that the output pulse width extends substantially. When the pulse width of the output pulse signal is broader than that of the input pulse signal, the signal is overlapped during a high speed operation.